This invention pertains generally to data processing systems and specifically to digital computer systems adapted to be modified to be used in many different applications.
It has been a prime objective of designers of digital computer systems to arrange the major components of such systems in a manner that the particular types of major components actually incorporated in a given system may be changed as desired for different applications. To permit such desired flexibility, it is well known to interconnect selected major components of a digital computer to terminals on a common bus and to provide bus control signals to direct the flow of data between selected ones of such components in a manner required for execution of a given program. With major components so interconnected, changes in the character and number of major components may easily be made as desired.
Although the principle of connecting major components of a digital computer system to a common bus is extremely simple, implementation of such a concept, without degradation of speed or accuracy of the system, is very difficult. First of all, operational characteristics of different types of major components, e.g. memory, arithmetic unit and peripheral equipment, of any digital computer system differ radically. It follows then, even in the simplest case, that the bus control signals generated during execution of a program must be adapted to the diverse operating characteristics of such different major components as are incorporated in any given digital computer system. Further, it is evident that, during execution of any program, the amount and character of information transferred between different major components by way of a common bus varies as any particular program is being executed. Obviously, therefore, the bus control signals generated during execution must be such that the order and manner of transmission of information may be varied to attain the most efficient execution of the program. The more sophisticated the computer system, the more important it is that the order of transmission of information between major components be properly controlled. Still further, it is mandatory in any digital computer system that the process of transferring each "unitary block" of information, say each digital word, from one major component to another includes verification procedures. That is, whenever a unitary block of information is to be transferred from one major component, say a memory, to another major unit, say an arithmetic unit, it is necessary to verify the fact that the desired transfer has been properly effected. Such verification may be accomplished by causing an "acknowledgment" signal to be returned over the common bus from the receiving component to the major component transmitting a unitary block of data. In response to the particular acknowledgment signal so returned to the transmitting major component, operation of such component (or the complete system) may then be continued or modified. Still further, if a digital computer system of any type is to be operated under adverse environmental conditions, it is necessary that means be provided to reduce the probability of system failure due to failure of the common bus.
In addition to the foregoing general requirements for any digital computer system incorporating different major components on a common bus, other requirements arise when operational speed is high or the major components are separated by any appreciable distance. In either such case, transmission delays suffered by synchronizing clock pulses between major components may become an appreciable portion of the time between successive ones of such clock pulses. To avoid difficulty, therefore, it is necessary that the common bus control signals be unaffected by transmission delays. Still further, when complex operations, as a "matrix multiply" operation, are to be executed it is highly desirable that only the major components used to execute such an operation be interconnected over a bus to interchange blocks of information. That is, there are occasions when a bus should be "dedicated"; it is highly desirable, therefore, that any bus control arrangement be adapted to permit many blocks of information to be transferred between designated major components to the exclusion of other major components in a digital computer system.
Many different approaches have been taken to solve the practical problems connected with common bus arrangements for digital computer systems. For example, it is known to provide a bus control arrangement based on a so-called "handshaking" principle. In arrangements of this type if information is to be transmitted from one major component to another, the receiving component is addressed so that an acknowledgment signal, i.e. a "busy" or "not busy" signal, may be generated and returned. Whether or not information may be transferred, time it taken to establish the status of the receiving major component, thus reducing the length of time for the desired transfer for information. To put it another way, the speed of operation of the system is reduced. To eliminate the delays inherent in "handshaking" it is known to provide bus control arrangements based on a so-called "time-slot" principle. In some known arrangements of such sort, each major component is permitted to transmit during a period between common synchronizing pulses applied to all, i.e. during a time slot. The simplest way to determine which major component may be transmitting is to assign, or dedicate, particular time slots to each different component. It follows, then, that in any given time slot, one (and only one) major component is allowed to transmit information. Such an approach results in faster operation than is possible with handshaking but is not ideal. Obviously, there will be many occasions in the execution of a program of almost any complexity when bus use requirements differ between the major components. It follows, then, that there are time slots during which the bus may not be used even though a major component is conditioned to transfer information. To increase efficiency in a "time-slot" bus control arrangement, it is known to provide a bus control arrangement based on a "nondedicated time-slot" principle. In such known arrangements the requisite bus control circuitry is ordinarily disposed in a so-called central controller and is arranged: (a) to poll the major components in a digital computer system to determine which ones of such components are conditioned to send or receive; and, then, (b) to provide an enabling signal to the major component next permitted to transmit. Known circuitry to accomplish such operations is, however, relatively complex and subject to failure. Further, with a central bus control arrangement, the physical location of the various components may limit operation. Because of transmission time delays suffered by any signal passing from one point to another, the distance of the major components in a digital computer system operating at high speed and using a central bus control arrangement may result in excessive delays affecting synchronization of the various major components.